Turn-key printed circuit board assembly

Publish Date:2020-11-14
  1. Whether the data received in the process is complete (including a schematic diagram, *. BRD documents, bill of materials, PCB design description, PCB design or change requirements, standardization requirements, and process design specifications);
  2. Confirm that the turn-key printed circuit board assembly template is up-to-date;
  3. Confirm the position of the positioner of the template is correct;
  4. Whether the PCB design specification, PCB design or change requirements and standardization requirements are clear;
  5. Confirm that the no placement device and wiring area on the outline drawing has been reflected on the PCB template;
  6. Compare the outline drawing to confirm that the dimension and tolerance marked by PCB are correct, and the definition of the metalized hole and the nonmetallic hole is accurate;
  7. After confirming that the turn-key printed circuit board assembly template is correct, it is better to lock the structure file to avoid misoperation and being moved
  8. Post layout inspection phase;
Turn-key printed circuit board assembly

Device inspection

Confirm whether all device packages are consistent with the company’s unified library and whether the package library has been updated (check the running results with ViewLOG). If not, update symbols;

The motherboard and the daughterboard, the single board and the backboard, confirm that the signal is corresponding and the position is corresponding, the direction of the connector and the silkscreen mark are correct, and the daughterboard has anti misinsertion measures, and the devices on the sub-board and the motherboard should not interfere;

Whether the components are placed 100%:

Open the place bound of the top and bottom layers of the device to see whether the DRC caused by overlap is allowed

Whether mark point is enough and necessary;

Heavy components should be placed close to the PCB support point or support edge to reduce PCB warpage;

It is better to lock the devices related to the structure after they are arranged to prevent misoperation;

Within 5mm around the crimping socket, no component with height higher than that of the crimp socket is allowed on the front side, and no component or solder joint is allowed on the back side;

Whether the placement of bgcc and bgcc meets the process requirements of PLA

For components with metal shell, special attention shall be paid not to collide with other components, and enough space shall be reserved;

Interface related devices shall be placed as close to the interface as possible, and the backplane bus driver shall be placed as close as possible to the backplane connector;

Whether chip device on wave soldering surface has been converted into wave soldering package;

Whether there are more than 50 manual solder joints;

If the components with higher height are inserted axially on PCB, horizontal installation should be considered. Leave room for sleeping. And the fixed mode, such as the fixed pad of crystal oscillator, is considered;

For devices that need to use a heat sink, make sure there is enough space between them and other devices, and pay attention to the height of main components within the range of heat sink;

Functional check

Whether the digital circuit and analog circuit device layout of the digital-analog mixing board have been separated, and whether the signal flow is reasonable;

The A / D converter is placed across a / D partition;

Whether the clock device layout is reasonable;

Whether the layout of high-speed signal devices is reasonable;

Whether the termination devices have been properly placed (the source matching series resistance should be placed at the driving end of the signal; the middle matching series resistance should be placed in the middle position; the terminal matching series resistance should be placed at the receiving end of the signal);

Whether the number and position of decoupling capacitors of IC devices are reasonable;

The signal line takes the plane of different levels as the reference plane. When the signal line crosses the plane partition area, whether the connecting capacitance between the reference planes is close to the signal routing area;

Whether the layout of the protection circuit is reasonable and conducive to segmentation;

Whether the fuse of the single-board power supply is placed near the connector and there is no circuit element in front of it;

Confirm that the strong signal circuit and the weak signal circuit (power difference 30dB) are arranged separately;

Whether the devices that may affect the EMC test are placed according to the design guidelines or referring to a successful experience. For example, the reset circuit of the panel should be slightly close to the reset button;


The heat-sensitive components (including a liquid dielectric capacitor and crystal oscillator) should be kept away from high-power components, heat sinks, and other heat sources as far as possible;

Whether the layout meets the requirements of thermal design and the cooling channel (according to the process design documents);

Power Supply

Whether the IC power supply is too far from the IC;

Whether the layout of LDO and its surrounding circuits is reasonable;

Whether the circuit layout around the module power supply is reasonable;

Whether the overall layout of power supply is reasonable;

Rule setting

Whether all simulation constraints have been added to the constraint manager correctly;

Whether the physical and electrical rules are set correctly (pay attention to the constraint setting of power network and ground network);

Whether the spacing of test via and test pin is enough;

Whether the thickness and scheme of lamination meet the design and processing requirements;

Whether the impedance of all differential lines with characteristic impedance requirements has been calculated and controlled by rules;

Post wiring inspection stage;

Mathematical model

Whether the wiring of the digital circuit and the analog circuit has been separated, and whether the signal flow is reasonable;

If a / D, D / A, and similar circuits are divided into ground, whether the signal line between the circuits goes from the bridge point between the two places (except for differential line);

The signal line that must cross the gap between the split power supplies should refer to the complete ground plane;

If the stratigraphic design partition is not divided, it is necessary to ensure that the digital signal and analog signal are zoned;

Clock and high speed part;

Whether the impedance layers of high-speed signal line are consistent;

Whether the high-speed differential signal line and similar signal line are running in equal length, symmetry and near parallel;

Make sure the clock line is in the inner layer as far as possible;

Confirm whether the clock line, high-speed line, reset line and other strong radiations or sensitive lines have been wired according to the 3W principle as far as possible;

Whether there are no test points on the clock, interrupt, reset signal, 100M / Gigabit Ethernet and high-speed signal ;

Whether the LVDS and other low-level signals and TTL / CMOS signals meet 10has far as possible (H is the height of the signal line from the reference plane);

Whether the clock line and high-speed signal line should not pass through the through-hole area of dense through holes or between device pins;

Eight Whether the clock line has met the (Si constraint) requirements (whether the clock signal routing is less through holes, short routing and continuous reference plane, and the main reference plane should be GND as far as possible; if the GND main reference plane layer is changed during layer change, the GND vias are within 200mil away from the via hole; if the main reference plane of different levels is changed during the layer change, whether there is decoupling within 200mil from the via hole (2) capacity;

Whether the differential pair, high-speed signal line and all kinds of bus have met the (Si constraint) requirements;

EMC and reliability

Turn-key printed circuit board assembly

For the crystal oscillator, whether a layer of ground is laid under the crystal oscillator; whether the signal line crossing between the device pins is avoided; for the high-speed sensitive device, whether the signal line is avoided from crossing the device pins;

There should be no acute angle or right angle on the signal line of the single board (generally it turns continuously at an angle of 135 degrees. The RF signal line is better to use the arc shape or the angle cutting copper foil after calculation);

For the double-sided board, check whether the high-speed signal line is closely connected with its return ground wire; for the multi-layer board, check whether the high-speed signal line is close to the ground plane as far as possible;

For the signal routing of two adjacent layers, try to route vertically as far as possible;

Avoid the signal line passing through the power module, common mode inductor, transformer, and filter;

Avoid long-distance parallel routing of high-speed signals on the same layer as far as possible;

Whether there are shielding vias at the edge of the board, such as digital, analog, and protective ground; whether multiple ground planes are connected by vias; whether the distance between vias is less than 1 / 20 of the highest frequency signal wavelength;

Whether the signal wiring corresponding to surge suppression device is short and thick on the surface;

Confirm that the power supply and stratum are free from the island, large slotting, long-horizon cracks, thin strip, and narrow channel caused by too large or dense through holes;

Whether the ground vias are placed at the places where the signal lines cross more floors (at least two ground planes are required)

Power and ground;

If the power/ground plane is divided, try to avoid the high-speed signal crossing on the separated reference plane;

Make sure that the power supply and ground can carry enough current. Whether the number of vias meets the bearing requirements (estimation method: the line width is 1A / mm when the thickness of outer copper is 1oz, the line width of the inner layer is 0.5a/mm, and the current of the short line is doubled);

Whether the power supply with special requirements meets the requirements of voltage drop;

In order to reduce the edge radiation effect of the plane, the 20h principle should be satisfied between the power layer and the stratum as far as possible;

If there is land division, whether the divided land does not form a loop;

Whether the overlapping placement is avoided in different power planes of adjacent layers;

Whether the isolation of the protected area, – 48V ground and GND is greater than 2mm;

Whether the – 48V ground is only the – 48V signal return, and it is not connected to other places; if not, please explain the reason in the remarks column;

Whether 10 ~ 20 mm protective ground is arranged near the panel with connector, and the layers are connected by double row staggered holes;

Whether the distance between the power line and other signal lines meets the requirements of safety regulations;

Forbidden area

There shall be no wiring, copper skin and via hole that may cause short circuit under metal shell devices and radiator parts;

There should be no wiring, copper skin and via hole that may cause short circuit around the installation screw or washer;

Whether there is wiring in the reserved position in the design requirements;

The distance between the inner layer of the non-metalized hole and the wire and copper foil should be greater than 0.5mm (20MIL) and the outer layer should be 0.3mm (12mil). The distance between the inner layer and the wire and copper foil in the shaft hole of the single board pull-out wrench should be greater than 2mm (80mil);

The copper sheet and wire to plate edge are recommended to be larger than 2mm and the minimum is 0.5mm;

The copper skin of the inner stratum is 1 ~ 2 mm from the plate edge, and the minimum is 0.5 mm;

Pad outlet

For chip components (package 0805 and below) installed on two pads, such as resistance and capacitance, the printed wire connected to the pad should be symmetrically led out from the center of the pad, and the printed wire connected to the pad must have the same width. For the outgoing line with the line width less than 0.3mm (12mil), this provision can be ignored

For the pad connected with wider printed wire, it is better to transition through a narrow printed wire in the middle (package 0805 and below);

The circuit should be led out from both ends of the pad of SOIC, PLCC, QFP, sot, etc;

Silk screen printing

Whether the device tag number is missing and whether the position can correctly identify the device;

Whether the device tag number meets the company standard requirements;

Confirm the correctness of the pin arrangement sequence, the first pin mark, the polarity mark of the device, and the direction mark of the connector;

Whether the direction marks of the boards of motherboard and daughterboard are corresponding;

Whether the backplane is correctly marked with slot name, slot number, port name, and sheath direction;

Confirm whether the silk screen printing required by the design is added correctly;

Make sure that the anti-static and radiofrequency board identification has been placed (for the use of radiofrequency board);

Code / barcode

Confirm PCB code is correct and conform to company specification;

Confirm that the PCB code position and layer of the board are correct (it should be on the upper left of side a, silkscreen layer);

Confirm that the PCB code position and layer of the backplane are correct (it should be on the top right of B, the outer copper foil surface);

Confirm that there is a white screen-printing area for barcode laser printing;

Make sure that there is no wire or through-hole larger than 0.5mm under the bar code frame;

Make sure that there are no components with a height of more than 25 mm within 20 mm outside the white screen printing area of the bar code;


  1. On the reflow soldering surface, vias should not be designed on the pad (the distance between the via of the normally opened window and the pad should be greater than 0.5mm (20MIL), and the distance between the via covered with green oil and the pad should be greater than 0.1 mm (4mil). Methods: open the same net DRC, check the DRC, and then close the same net DRC);
  2. The arrangement of vias should not be too close to avoid causing large-scale fracture of power supply and ground plane;
  3. The through-hole diameter of the drilling hole should not be less than 1 / 10 of the plate thickness;
  4. Whether the device layout rate is 100% and whether the device pass rate is 100% (if it does not reach 100%, it needs to be explained in the remarks);
  5. Whether the dangling lines have been adjusted to the minimum, and the reserved dangling lines have been confirmed one by one;
  6. Whether the process problems fed back by the process department have been checked carefully;
    Large area copper foil
  7. For large area copper foil on top and bottom, if there is no special need, grid copper (inclined mesh for veneer, orthogonal mesh for backplane, width 0.3mm (12 mils), spacing 0.5mm (20MIL));
  8. The component pad in the large area of copper foil area should be designed as a fancy pad to avoid false soldering; if there is a current requirement, the reinforcement of the solder pad should be widened first, and then the full connection should be considered;
  9. When copper is distributed in a large area, dead copper (isolated island) without network connection should be avoided as far as possible;
  10. Pay attention to whether there are illegal connection and unreported DRC in large area copper foil;
    Test point
  11. Whether the test points of various power sources and ground are sufficient (at least one test point for every 2A current);
  12. Confirm that the network without test points can be simplified after confirmation;
  13. Confirm that no test points are set on the plug-ins that are not installed during production;
  14. Whether the test via and test pin have been fixed (applicable to the change plate with the same needle bed);
  15. The spacing rule of the test via and test pin should be set to the recommended distance to check DRC. If DRC still exists, check DRC with minimum distance setting;
  16. Set the open constraint to the open state, update the DRC, and check whether there are disallowed errors in the DRC;
  17. Confirm that the DRC has been adjusted to the minimum, and confirm that the DRC cannot be eliminated one by one;
    Optical positioning point
  18. Confirm that there are optical positioning symbols on the PCB surface with mounting components;
  19. Confirm that the optical positioning symbol is not embossed (silk screen printing and copper foil routing);
  20. The background of the optical positioning point should be the same, and the center of the optical point should be no less than 5mm from the edge;
  21. Confirm that the coordinate value has been assigned to the optical positioning reference symbol of the whole board (it is recommended to place the optical positioning reference symbol in the form of the device) and it is an integer value in mm.
  22. For IC with pin center distance less than 0.5 mm and BGA device with a center distance less than 0.8 mm (31 mils), optical positioning points should be set near the component diagonal;
    Resistance welding inspection
  23. Confirm whether the pads with special requirements are properly windowed (pay special attention to the hardware design requirements);
  24. Whether the through-hole under BGA is treated as a cover oil plug hole;
  25. Whether small windows or oil plug holes have been made for vias other than test vias;
  26. Whether the windows of optical positioning points avoid copper and wire exposure;
  27. Whether the power chip, crystal oscillator, and other devices that need copper skin heat dissipation or grounding shielding have copper skin and open windows correctly. The devices fixed by solder should have green oil to block the large area diffusion of solder;
    Processing documents
    Borehole map
  28. Whether the PCB thickness, layer number, screen printing color, warpage, and other technical specifications of notes are correct;
  29. Whether the layer name, stacking sequence, medium thickness, and copper foil thickness of the stack diagram are correct; whether the impedance control is required and whether the description is accurate; whether the layer name of the stack diagram is consistent with the photo drawing file name;
  30. Turn off the repeat code in the setting table and set the drilling accuracy to 2-5;
  31. Whether the hole table and drilling file are up-to-date (must be regenerated when changing holes);
    Whether there is the correct hole diameter in the pressure connection; 5;
  32. Whether the vias to be plugged are listed separately and marked with “filled vias”;
Turn-key printed circuit board assembly

Light painting

Rs274x format should be used as far as possible for photo file output, and the precision should be set to 5:5

art_ aper.txt Is it up to date (274x may not be required)

Is there any exception report in the log file of output photo file

Confirm the edge and island of negative layer

Use photo inspection tool to check whether the photo file is consistent with PCB (the comparison tool shall be used for comparison when modifying the board)
Complete set of documents

PCB file: product model_ Specifications_ Veneer code_ Version number.brd;

Design document of backing plate: product model_ Specifications_ Veneer code_ Version number – CB [- t / b]. BRD;

PCB processing file: PCB (including light drawing file, aperture table, drilling file, and ncdrill.log For the panel, the panel file. DXF provided by the process is required, and the backing board file: PCB code – CB [- t / b]. Zip (including a 、.drl、 ncdrill.log );

Process design document: product model_ Specifications_ Veneer code_ Version number- GY.doc ;

SMT coordinate file: product model_ Specifications_ Veneer code_ Version number- SMT.txt (when outputting the coordinate file, confirm to select body center, and only select symbol origin when confirming that the origin of all SMD device libraries is the device center);

PCB structure file: product model_ Specifications_ Veneer code_ Version number- (including structure. DXF and. EMN files provided by the Engineer);

Test document: product model_ Specifications_ Veneer code_ Version number- TEST.ZIP (contains testprep.log And untested. First Or *. DRL test point coordinate file);

Filing drawings and documents: product model and specification – board name – version number.pdf (including cover, front page, silk screen printing of each layer, the circuit of each layer